PCI Command/Status Register

The PCI Command register is part adapter PCI Configuration space as defined by PCI standard 2.2. and it provides basic control over the devices ability to respond to and /or perform PCI accesses.

The command register is a 16 bit register with bit 9 to 0 current defined.
Bit 10 to 15 are currently reserved and must be set to zero. These registers are set up a configuration time and indicate how the adapter was configured

The PCI status/CMD regs are dumped for error attentions

The PCI Status register tracks the function's status of a PCI entity.
The PCI status register is a 16 bit register. Currently (PCI 2.2) bits 4 to 5 and bits 7 to 15 are defined with bits 0 to 3 and bit 6 reserved.
- 0x30 - may indicate an adapter problem and
- on EEH freeze events (0x50 - indicates a problem with the PCI slot, AIX device driver or adapter hardware)

The Command Register DETAIL SENSE DATA
Here below is a cut from the full error log sense template. Click here to see full error template.

AIX Version 5.3 and below

RRRR RRRR EEEE EEEE TTCC OOOO NNNN NNNN NNNN NNNN IIII IIII MMMM MMMM LLLL LLLL
AAAA AAAA BBBB BBBB DDDD DDDD FFFF FFFF GGGG GGGG HHHH HHHH JJJJ JJJJ KKKK KKKK
PPPP PPPP SS%% UUUU VVVV VVVV WWWW WWWW XXXX XXXX YYYY YYYY ZZZZ ZZZZ 2222 2222
3333 3333 4444 4444 QQQQ QQQQ PCIC PCIS QQQQ QQQQ QQQQ QQQQ QQQQ QQQQ QQQQ QQQQ
....

AIX Version 6 and above:

hhhh hhhhh EEEE EEEE TTCC vvvv NNNN NNNN NNNN NNNN IIII IIII MMMM MMMM LLLL LLLL
AAAA AAAA BBBB BBBB DDDD DDDD FFFF FFFF GGGG GGGG HHHH HHHH JJJJ JJJJ KKKK KKKK
PPPP PPPP SS%% UUUU VVVV VVVV WWWW WWWW XXXX XXXX YYYY YYYY ZZZZ ZZZZ 2222 2222
3333 3333 4444 4444 5555 5555 5555 RRRR 7777 7777 7777 7777 RRRR RRRR RRRR RRRR OOOO RRRR....
..skip 5 rows RRRR Reserved for future use.
QQQQ QQQQ PCIC PCIS next 22 rows

The command register "PCIC "PCI assignments are:

Bit	Word	Function Description
0	0000 0000 0000 0001	IO Space enabled when bit is set
1	0000 0000 0000 0010	Memory Space enabled when bit is set
2	0000 0000 0000 0100	Bus Master enabled when bit is set
3	0000 0000 0000 1000	Special Cycles enabled when bit is set
4	0000 0000 0001 0000	Memory Write and Invalidate enabled when bit is set
5	0000 0000 0010 0000	VGA Palette Snoop enabled when bit is set
6	0000 0000 0100 0000	Parity Error Response. When set, the device can report a PCI bus parity error (by asserting PERR#
7	0000 0000 1000 0000	Stepping Control, When this bit is set, the device can perform address/data stepping
8	0000 0001 0000 0000	SERR# Enable. When this bit is set, the device can driver the SERR# line.
9	0000 0010 0000 0000	Fast Back-to-Back Enable. When set, the bus master is capable of performing Fast Back-to Back transactions
10-15	1111 1100 0000 0000	Reserved. These bits must not be set

The PCI Status Register

The PCI Status register assignments "PCIS" are:

Bit	Word	Description	What to do
0-3	0000 0000 0000 1111	Reserved	These bits should not be set
4	0000 0000 0001 0000	Capabilities list. When set, the capabilities list pointer configuration register is implemented	Information only
5	0000 0000 0010 0000	66 MHz-Capable	Information only
6	0000 0000 0100 0000	Reserved	This bit should not be set
7	0000 0000 1000 0000	Fast Back to Back Capable when set	Information only
8	0000 0001 0000 0000	Data Parity Error	Replace the adapter
1-10	0000 0110 0000 0000	Device Select (DEVSEL#) Timing. Define the slowest DEVSEL# timings for a target device 00b = fast 01b = medium 10b = slow 11b = reserved	Information only
11	0000 1000 0000 0000	Signaled Target Abort	In this problem persists, Contact IOPE
12	0001 0000 0000 0000	Received Target Abort	Contact IOPE
13	0010 0000 0000 0000	Received Master Abort	Contact IOPE
14	0100 0000 0000 0000	Received System Error (SERR#)	Contact IOPE
15	1000 0000 0000 0000	Detected Parity Error	Replace the adapter